The present invention relates to integrated circuit (IC) designs, and more particularly to a method and a system for improving the reliability of memory device.
A memory device typically includes a number of memory banks coupled with a number of circuit modules that control the operation of those memory banks. The memory bank usually includes a number of memory cells arranged in rows and columns for data storage. Besides the regular memory cell rows, the memory bank would also include one redundant memory cell row that has the same number of memory cells as the regular memory cell row. The redundant memory cell row is conventionally reserved for replacing the regular memory cell row that is defective. The replacement can be done by readdressing the defective regular memory cell row to the redundant memory cell row without physically rerouting the wiring of the memory device.
Conventionally, the redundant memory cell row is used only when the regular memory cell row is defective. While a regular memory cell row passing the minimal functionality test is not defective, it may be unreliable. The unreliable regular memory cell row may fail after a few hundred operation cycles and cause problems to the memory device. Thus, the conventional scheme, which cannot utilize the redundant memory cell rows to replace the unreliable but non-defective regular memory cell rows, has no effect on the reliability of the memory device.
Moreover, the conventional scheme is typically carried out using an external testing apparatus, instead of a circuit module embedded on the memory device. This is very time-consuming and cost inefficient.
It is therefore desirable to have a method and system for more efficiently utilizing the redundant memory cell rows to improve the reliability of the memory device.